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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i_o_module___vector_table_entry.html">XIOModule_VectorTableEntry</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Defines the number of timer counters within a single hardware device.  <a href="struct_x_i_o_module___vector_table_entry.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga230620599fe987b03b47e6d04a442e60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga230620599fe987b03b47e6d04a442e60">XIOModule_EnableIntr</a>(BaseAddress, EnableMask)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))</td></tr>
<tr class="memdesc:ga230620599fe987b03b47e6d04a442e60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable specific interrupt(s) in the interrupt controller.  <a href="group__iomodule.html#ga230620599fe987b03b47e6d04a442e60">More...</a><br/></td></tr>
<tr class="separator:ga230620599fe987b03b47e6d04a442e60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf77d72d553f17c2696ce54e3149f0d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#gaaf77d72d553f17c2696ce54e3149f0d0">XIOModule_DisableIntr</a>(BaseAddress, DisableMask)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))</td></tr>
<tr class="memdesc:gaaf77d72d553f17c2696ce54e3149f0d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable specific interrupt(s) in the interrupt controller.  <a href="group__iomodule.html#gaaf77d72d553f17c2696ce54e3149f0d0">More...</a><br/></td></tr>
<tr class="separator:gaaf77d72d553f17c2696ce54e3149f0d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3f5aa29d205f6221a017a04712c65f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#gac3f5aa29d205f6221a017a04712c65f0">XIOModule_AckIntr</a>(BaseAddress, AckMask)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))</td></tr>
<tr class="memdesc:gac3f5aa29d205f6221a017a04712c65f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge specific interrupt(s) in the interrupt controller.  <a href="group__iomodule.html#gac3f5aa29d205f6221a017a04712c65f0">More...</a><br/></td></tr>
<tr class="separator:gac3f5aa29d205f6221a017a04712c65f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga128f261df0c50d6e1b090e2a9e9d1874"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga128f261df0c50d6e1b090e2a9e9d1874">XIOModule_GetIntrStatus</a>(BaseAddress)&#160;&#160;&#160;(XIomodule_In32((BaseAddress) + XIN_IPR_OFFSET))</td></tr>
<tr class="memdesc:ga128f261df0c50d6e1b090e2a9e9d1874"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the interrupt status from the interrupt controller which indicates which interrupts are active and enabled.  <a href="group__iomodule.html#ga128f261df0c50d6e1b090e2a9e9d1874">More...</a><br/></td></tr>
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<tr class="memitem:ga313c2576e159fd472cb0b25b7a395837"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga313c2576e159fd472cb0b25b7a395837">XIOModule_GetStatusReg</a>(BaseAddress)&#160;&#160;&#160;XIomodule_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)</td></tr>
<tr class="memdesc:ga313c2576e159fd472cb0b25b7a395837"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the contents of the UART status register.  <a href="group__iomodule.html#ga313c2576e159fd472cb0b25b7a395837">More...</a><br/></td></tr>
<tr class="separator:ga313c2576e159fd472cb0b25b7a395837"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9c5e48a02c0aba03cb1d8d7583b37f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#gad9c5e48a02c0aba03cb1d8d7583b37f6">XIOModule_IsReceiveEmpty</a>(BaseAddress)</td></tr>
<tr class="memdesc:gad9c5e48a02c0aba03cb1d8d7583b37f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check to see if the UART receiver has data.  <a href="group__iomodule.html#gad9c5e48a02c0aba03cb1d8d7583b37f6">More...</a><br/></td></tr>
<tr class="separator:gad9c5e48a02c0aba03cb1d8d7583b37f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93c23372164e627f79da9488ea43161a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga93c23372164e627f79da9488ea43161a">XIOModule_IsTransmitFull</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga93c23372164e627f79da9488ea43161a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check to see if the transmitter is full.  <a href="group__iomodule.html#ga93c23372164e627f79da9488ea43161a">More...</a><br/></td></tr>
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<tr class="memitem:ga829c77e3efe996211599f9a2a6bb4890"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga829c77e3efe996211599f9a2a6bb4890">XIOModule_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga829c77e3efe996211599f9a2a6bb4890"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a value to a GPO register.  <a href="group__iomodule.html#ga829c77e3efe996211599f9a2a6bb4890">More...</a><br/></td></tr>
<tr class="separator:ga829c77e3efe996211599f9a2a6bb4890"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eaff234e65f369a870fca3b92215df4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga4eaff234e65f369a870fca3b92215df4">XIOModule_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XIomodule_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga4eaff234e65f369a870fca3b92215df4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a value from a GPI register.  <a href="group__iomodule.html#ga4eaff234e65f369a870fca3b92215df4">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga6e89f42ede1324eaf70720f6db6783b4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga6e89f42ede1324eaf70720f6db6783b4">XIOModule_SendByte</a> (UINTPTR BaseAddress, u8 Data)</td></tr>
<tr class="memdesc:ga6e89f42ede1324eaf70720f6db6783b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This functions sends a single byte using the UART.  <a href="group__iomodule.html#ga6e89f42ede1324eaf70720f6db6783b4">More...</a><br/></td></tr>
<tr class="separator:ga6e89f42ede1324eaf70720f6db6783b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae5eea17f7c7533affa36870f94f6299"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#gaae5eea17f7c7533affa36870f94f6299">XIOModule_RecvByte</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:gaae5eea17f7c7533affa36870f94f6299"><td class="mdescLeft">&#160;</td><td class="mdescRight">This functions receives a single byte using the UART.  <a href="group__iomodule.html#gaae5eea17f7c7533affa36870f94f6299">More...</a><br/></td></tr>
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<tr class="memitem:ga2e47bfda481c3ceab60d758f049758ef"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga2e47bfda481c3ceab60d758f049758ef">XIOModule_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr class="memdesc:ga2e47bfda481c3ceab60d758f049758ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the primary interrupt handler for the driver.  <a href="group__iomodule.html#ga2e47bfda481c3ceab60d758f049758ef">More...</a><br/></td></tr>
<tr class="separator:ga2e47bfda481c3ceab60d758f049758ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b99cc28b7c0282919f3039d8d60e168"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#ga9b99cc28b7c0282919f3039d8d60e168">XIOModule_SetIntrSvcOption</a> (UINTPTR BaseAddress, s32 Option)</td></tr>
<tr class="memdesc:ga9b99cc28b7c0282919f3039d8d60e168"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs.  <a href="group__iomodule.html#ga9b99cc28b7c0282919f3039d8d60e168">More...</a><br/></td></tr>
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<tr class="memitem:gab55e07c2159c0c0b469503bfac8e20b0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule.html#gab55e07c2159c0c0b469503bfac8e20b0">XIOModule_RegisterHandler</a> (UINTPTR BaseAddress, s32 InterruptId, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr class="memdesc:gab55e07c2159c0c0b469503bfac8e20b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a handler function for a specific interrupt ID.  <a href="group__iomodule.html#gab55e07c2159c0c0b469503bfac8e20b0">More...</a><br/></td></tr>
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